1. Field of the Invention
The present invention relates to field programmable gate array (FPGA) circuits. More particularly, the present invention relates to implementing a fast wide decode circuit in an FPGA using probe circuitry present in the FPGA for testing.
2. The Prior Art
Digital addressing schemes and decoding of digital addresses are well known in the art. In many of these addressing schemes, specific addresses are decoded to access a single device in a system. For example, in a computer system specific addresses are provided to access internal memory, external memory, peripherals, etc. Since many of these devices are accessed frequently, it is advantageous to decode the addresses for these devices quickly. Often, the addresses in conventional addressing schemes are represented by 8 to 64 bits. Thus, it is advantageous for the decoding circuitry of an often used address to not only be fast, but to also be wide enough to process all of the bits in the address.
FPGA's typically are comprised of identical logic modules which may be programmed to provide specific logic functions. The inputs and outputs of the logic modules are connected to one another, and to I/O pads and I/O buffers, etc., by an interconnect architecture scheme. It is well known in the art that FPGA's are employed to form custom circuits and to design circuits for more general use. These circuits often require the fast, wide decode of an address as described above. In FPGA's there have been at least two approaches to providing a fast, wide decode.
In one approach, for example, to quickly decode a 32-bit address, several of the logic function modules will be programmed so that the inputs and outputs of the logic modules correspond to the desired address. When the logic modules in the FPGA have 4 inputs and a single output, a total of eleven logic modules are required to decode a 32-bit address. In a typical addressing scheme, eight logic modules will be used to observe the address, and the outputs of the eight logic modules will be cascaded into two additional logic modules whose outputs will be further cascaded into another module whose output will be connected to an I/O pad. This decoding scheme requires a substantial number of logic modules, and the speed of the decode is less than ideal.
In another approach, the eight 4-bit input logic modules may be cascaded into a special 8-input-wide module whose output is connected to an output pad. Though this alternative improves the speed of the decode, the 8-input logic module utilizes a substantial amount of routing resources to function.
It is therefore an object of the present invention to provide a fast, wide address decode which reduces the delay in the decoding.
It is another object of the present invention to provide a fast, wide address decode which utilizes routing resources implemented for a test probe feature.